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|Title=Design of gate array circuits using evolutionary algorithms | |Title=Design of gate array circuits using evolutionary algorithms | ||
|Year=2008 | |Year=2008 | ||
| − | |Booktitle=International Conference on Architecture of Computing Systems | + | |Booktitle=International Conference on Architecture of Computing Systems |
|Pages=38-50 | |Pages=38-50 | ||
|Publisher=Springer | |Publisher=Springer | ||
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fitness assignment as well as the area cross-over operator considerably | fitness assignment as well as the area cross-over operator considerably | ||
improve the performance of the evolutionary optimisation. | improve the performance of the evolutionary optimisation. | ||
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Aktuelle Version vom 24. September 2009, 16:53 Uhr
Design of gate array circuits using evolutionary algorithms
Design of gate array circuits using evolutionary algorithms
Published: 2008
Buchtitel: International Conference on Architecture of Computing Systems
Ausgabe: 4934
Reihe: LNCS
Seiten: 38-50
Verlag: Springer
Referierte Veröffentlichung
BibTeX
Kurzfassung
In this paper, we study the design of combinational logic
circuits using evolutionary algorithms. In particular, this paper is about
fitness assignment methods and recombination operators for speeding
up the optimisation process. We propose a new fitness assignment mechanism
called MaxMin method and compare it with the straightforward
method used in the literature. The results show significant improvements
both in terms of computational time and quality of the solutions. Furthermore,
a new cross-over operator called area cross-over has been introduced
and compared with other typical operators. This operator is particularly
designed for gate matrices where two rectangular logic blocks
are exchanged between the individuals. We observe that the MaxMin
fitness assignment as well as the area cross-over operator considerably
improve the performance of the evolutionary optimisation.
Evolutionäre Algorithmen, FPGA