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|Abstract=Dynamically and partially reconfiguranle field-programmable gate arrays (FPGAs) allow to swap in and out tasks without interrupting the execution of other tasks. The FPGA controller can decide on-line where to place new tasks onto the FPGA. Rearranging a subset of the tasks executing on the FPGA may allow the next pending task to be processed sooner. When tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. In this paper, we describe and evaluate an evolutionary approach to solve the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. We use two genetic algorithms (GAs): one for iodentifying feasible rearrangements and the other for scheduling a selected rearrangement so that the delay caused by this rearrangement is small and the limited input buffer size is respected. | |Abstract=Dynamically and partially reconfiguranle field-programmable gate arrays (FPGAs) allow to swap in and out tasks without interrupting the execution of other tasks. The FPGA controller can decide on-line where to place new tasks onto the FPGA. Rearranging a subset of the tasks executing on the FPGA may allow the next pending task to be processed sooner. When tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. In this paper, we describe and evaluate an evolutionary approach to solve the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. We use two genetic algorithms (GAs): one for iodentifying feasible rearrangements and the other for scheduling a selected rearrangement so that the delay caused by this rearrangement is small and the limited input buffer size is respected. | ||
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Aktuelle Version vom 24. September 2009, 21:14 Uhr
An Evolutionary Approach to Dynamic Task Scheduling on FPGAs with Restricted Buffer
An Evolutionary Approach to Dynamic Task Scheduling on FPGAs with Restricted Buffer
Veröffentlicht: 2002 September
Journal: Journal of Parallel and Distributed Computing
Nummer: 9
Seiten: 1407-1420
Volume: 62
Referierte Veröffentlichung
Kurzfassung
Dynamically and partially reconfiguranle field-programmable gate arrays (FPGAs) allow to swap in and out tasks without interrupting the execution of other tasks. The FPGA controller can decide on-line where to place new tasks onto the FPGA. Rearranging a subset of the tasks executing on the FPGA may allow the next pending task to be processed sooner. When tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. In this paper, we describe and evaluate an evolutionary approach to solve the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. We use two genetic algorithms (GAs): one for iodentifying feasible rearrangements and the other for scheduling a selected rearrangement so that the delay caused by this rearrangement is small and the limited input buffer size is respected.
Evolutionäre Algorithmen, Rekonfigurierbarkeit, Rechnerarchitektur